1. Field of the Invention
The present invention relates to a non-volatile semiconductor device and particularly to an erasing circuit in a flash (entire array erasure type) EEPROM.
2. Description of the Related Art
Referring to FIG. 11, there is shown the circuit of a flash EEPROM constructed in accordance with the prior art. For simplification, the circuit is shown to comprise eight memory transistors. Actually, such a memory section is formed by a matrix in which a desired number of memory transistors are arranged. As shown in FIG. 13, if the memory section is of a large capacity, for example, equal to 256 Kbits, it is divided into blocks 135-138 each of which is equal to 64 Kbits. Blocks 139 and 140 each comprising X-decoder and other components are arranged between the divided blocks.
The circuit of the prior art shown in FIG. 11 comprises the memory transistors 1-8 and Nch and Pch transistors 205, 206 which are connected to the source areas of the memory transistors 1-8 through a source line SL. The gate electrodes of the transistors 205 and 206 receive an erase signal through an interface 223 and inverter 230. The interface 223 functions to convert the fluctuation of input voltage of Vdd-GND into the fluctuation of output voltage of Vpp-GND.
The control electrodes of the memory transistors 1-8 are connected to word lines WL1, WL2, WL3 and WL4, respectively. The drain areas of the memory transistors 1-8 are connected to bit lines BL1 and BL2.
An address signal is inputted into X- and Y-decoders 118, 94 through an address buffer 92. The X-decoder 118 then generates an X-decoder signal which is inputted into an interface 116. The interface 116 converts the fluctuation of input voltage of Vdd-GND of X-decoder signal into the fluctuation of output voltage of Vpp-GND, and a word line signal for the word line WL1-WL4 is generated. The Y-decoder 94 generates a Y-decoder signal which in turn is sent to a write and erase control circuit 119 and sense amplifier 96.
The write and erase control circuit 119 is controlled by the Y-decoder signal with respect to the write of data. More particularly, data inputted through a data buffer 98 is written in the memory transistors 1-8 by the write and erase control circuit 119 using the Y-decoder signal as an address. The write and erase control circuit 119 further controls to erase the data stored in the memory transistors 1-8.
The sense amplifier 96 reads out the data from the memory transistors 1-8 using the Y-decoder signal as an address. The data read out is outputted through the data buffer 98 as a data signal.
The circuit of the prior art will be described in more detail with reference to the potential diagram of FIG. 12.
First of all, the write operation will be described. When the write is to be made to the memory transistor 1, WL1 and BL1 are placed at high potential Vpp level while WL2, WL3, WL4 and BL2 are placed at GND level, as shown in FIG. 12. By further placing the erase signal at L, level (lower logical invert level), the Nch transistor 205 is turned on and the Pch transistor 206 is turned off. Thus, the source line SL is placed at GND level to generate a channel current in the memory transistor 1. As a result, hot electrons are produced at the drain area end of the memory transistor 1. By injecting the electrons into the floating gate electrode, the write will be carried out. At this time, the write will not be made in the other memory transistors 2-8 since no channel current is generated therein.
Next, the erase will be described. When the erase is to be made, WL1, WL2, WL3 and WL4 are placed at GND level while BL1 and BL2 are placed at open level, as shown in FIG. 12. By further placing the erase signal at H level (upper logical invert level), the Nch transistor 205 is turned off and the Pch transistor 206 is turned on. Thus, the source line SL is placed at Vpp level to generate a tunnel current between the floating gate electrode of each of the memory transistors 1-8 and its associated source area. As a result, electrons are released from the floating gate electrode to the associated source area to perform the erase operation.
When the erase operation is to be carried out in the memory transistors 1-8, the common source line is used and all the word lines are placed at GND level. Therefore, the prior art could perform only the simultaneous erasure of all the memory transistors, that is, entire array erasure. Even if the memory part is divided into blocks as shown in FIG. 13, the common source line is used through each of the divided blocks 135-138. Therefore, the erasure could be made only for each block at a time, for example, for every 64 Kbits (512.times.128 bits). For instance, Japanese Patent Application Laid-Open No. 3-230397 carries out the erase operation in a block manner.
The flash EEPROM is characterized by that it is non-volatile, writable and higher in capacity. Attention is paid to the flash EEPROM as a memory that can be used in place of magnetic disc, hard disc and the like. However, the flash EEPROM of the prior art is disadvantageous in that it can be erased only in the entire manner or for each block at a time. On the contrary, the hard disc or the like performs the write and erase of data for every 512 bytes in connection with the operating system of a computer. The replacement of the hard disc or the like requires a flash EEPROM that can perform the erasure for less bytes at a time.
The flash EEPROM or the prior art that can perform only the entire array erasure or block erasure has another problem in that an excess current flows on the erase operation. More particularly, if an excess current flows between the source and the substrate due to the entire array erasure, a so-called band-to-band tunneling will be generated to raise various problems such as change of threshold voltage Vth, degradation of endurance, degradation or data retention and so on.
The entire array erasure or block erasure raises a further problem in that the threshold voltage of the memory transistor can be fluctuated over very increased range after the erase operation. More particularly, since the erase operation is carried out by generating the tunnel current between the floating gate electrode and its associated source area as described, the variability from one memory transistor to another becomes larger. As the number of memory transistors to be erased at a time increases, the dispersion of threshold voltage distribution in one chip increases correspondingly. Particularly, if even one memory transistor in the chip is overerased and depleted by the distribution of threshold voltage after the erasure, a leak current will flow in a bit line connected to that memory transistor. As a result, the read-out operation may fail on reading a memory transistor connected to the bit line.